(1) Field of the Invention
The present invention relates to an apparatus and method for achieving a high-speed data read access to contiguous areas in noncachable memory such as frame buffers.
(2) Description of the Related Art
Cache memory has been commonly used in order to achieve high-speed data read access to memory. Cache memory was originally supplied to main memory to speed up its low access rate by the use of cache, but has recently been supplied, as disk cache memory, to secondary memory such as hard disk.
However, some memory or memory areas are not cachable depending on their usage. For example, a frame buffer which stores display data or image data to be displayed on a display device is not cachable because the contents of these data are directly displayed on the display device.
FIG. 1 shows the construction of a typical conventional apparatus for achieving high-speed data read access to noncachable memory.
In the illustration, the typical conventional apparatus 61 is provided with a bus address and control signal decoder 611, a memory address and control signal generator 612, a memory data controller 613, and a bus data controller 614, thereby controlling data access from a processor (not shown) to memory 62 via a system bus 60.
The bus address and control signal decoder 611 (hereinafter referred to as BA decoder 611) decodes the address and size of data sent through the system bus 60.
The memory address and control signal generator 612 (hereinafter referred to as MA generator 612) generates a row address and a column address, based on the results found out by the BA decoder 611, thereby sending it to the memory 62.
The memory data controller 613 (hereinafter referred to as MD controller 613) controls data input/output operations between the BD controller 614 and the memory 62.
The bus data controller 614 (hereinafter referred to as BD controller 614) controls data input/output operations between the MD controller 613 and the system bus 60.
The apparatus 61 provided with these components operates as follows.
FIG. 2 shows a time chart depicting a data readout operation carried out by the apparatus 61.
Receiving signals indicating the address and size of data to be accessed through the system bus 60, the BA decoder 611 decodes the signals. The MA generator 612 generates a row address and a column address, based on the results decoded by the BA decoder 611, thereby starting to access the memory 62. After a certain period of access time, data read out from the memory 62 are sent out to the system bus 60 through the MD controller 613 and the BD controller 614.
FIG. 3 shows a time chart depicting a data readout operation when data to be accessed are larger than the memory 62 in width. This case is called burst transmission, where the MA generator 612 performs page mode access by outputting serial column addresses on end to the memory 62. This allows a plurality of data to be sent out to the system bus 60 within a short time period.
As explained hereinabove, according to the conventional apparatus, control signals to the memory 62 are generated by the MA generator 612 in response to an access request sent through the system bus 60. And access to contiguous areas, which frequently occurs is controlled by page mode access, thereby achieving a high-speed data access.
However, the conventional apparatus has the following drawback.
Burst transmission is not requested on noncachable memory such as frame memory and VRAM, or noncachable memory area so that contiguous areas in such memory are accessed normally, demanding the same amount of time for each access. As a result, high-speed data access cannot be achieved.